Wissenschaftliche Publikationen "Elektronik"

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The current industrial revolution derives much of its momentum from value creation based on interconnected products and related data based services. Such products must fulfill both mechanical and electrical requirements, making them mechatronic systems. The production of such systems via additive manufacturing (AM) processes offers advantages in achievable complexity, reduction of the amount of individual components, and cost-effective as well as sustaina ble production of small quantities. In this work, a process chain is presented that allows for refining additively manufactured 3D structures made from industry-standard materials into mechatronic components by creating electrically conductive structures directly on their surfaces. The process chain is based on masking the component’s surface and selectively removing the masking according to the circuit geometry using laser radiation. In a wet–chemical bath process, the surface is then exposed to palladium nuclei, the masking is fully removed and metal layers (copper/nickel/gold) are deposited by electroless plating. The procedure is developed using stereolithography as a model process for AM and transferred to four additional AM methods. In all cases, despite markedly different surface properties, good selectivity of metal deposition is observed as well as adhesion strength and conductivity comparable to industrially common injection-molded laser direct structured mechatronic interconnect devices.

Schlussbericht "Fortschrittliche Glas-Interposer mit Carbon-Kupfer-Verbundmetallisierung" zu IGF-Vorhaben Nr. 337 EBG

• This work represents a CMOS-Based nanoporesensing platform for high resolution readout of nanoporeevents.
• CMOS integration reduces the overall capacitance of the readout which reduces the overall noise and thus allows detecting of fast and/or small nanoporeevents.
• The current readout circuit is configurable for different current ranges and bandwidths and optimized for noise suppression. The circuit is divided into four amplifier stages.
• Noise reduction techniques achieve a total integrated noise of only 18 pARMSin a bandwidth of 1 MHz.
• The ASIC was implemented in a 350 nm standard CMOS technology.
• The ASIC consists of five channels. Four of them are used as a MECA.

 

Link to paper